Design Approach for Decimation Filter for ADC Application

This paper presents a kind of design method about the decimation filter design for high performance ADC application. It was implemented and validated by simulation using MATLAB tool and its complete architecture was realized using DSP blockset and Simulink. A two-stage decimation filter architecture which can reduce digital switching noise was also introduced in this design. The FIR low pass filter is used for both the stages of the decimation filter as a anti-aliasing filtering process. The resulting architecture having increased computational efficiency, smaller size and high performance also it consumes less power as compared to conventional decimation filters. The design was simulated using MATLAB according to this scheme can achieve higher performances. Keywords— Digital Decimation Filter, ADC, FIR low pass filter, Comparator.